Original Link: https://www.anandtech.com/show/880
Intel's E7500 Chipset: Dual Channel DDR for Xeon
by Anand Lal Shimpi on February 25, 2002 3:00 AM EST- Posted in
- CPUs
Although an adamant supporter of RDRAM with many RDRAM based chipsets in the pipeline, Intel is still open to the use of competing memory technologies for their products. Contrary to popular belief, the world's largest CPU manufacturer is driven by engineering and one of the first principles an engineer follows is to do what makes sense.
There are a number of reasons that RDRAM doesn't make sense for the high-end server market all of which Intel has publicly admitted to and accepted. Thus it should come as no surprise to anyone that today Intel is announcing their return to volume Dual Processor server chipsets with the E7500; a chipset that not only uses DDR SDRAM, but dual channel DDR SDRAM in order to offer just as much (peak theoretical) memory bandwidth as Intel's RDRAM based offerings.
The E7500 announcement also shouldn't be a shock because we've actually reported about the chipset, albeit under a different name, for quite some time. The name Plumas has been floating around for a while and has finally taken form with the E7500. If you'll remember back to our coverage of Comdex 2001 in Las Vegas, we were presented with a handful of Plumas (E7500) based solutions back then which are now almost ready for prime time.
With this week being the beginning of the Spring 2002 Intel Developer Forum there is bound to be quite a bit of discussion about the E7500 chipset, its performance and what it means to server, workstation and desktop markets. This article provide you with a bit of an overview of the E7500 chipset and when I get back to the lab following IDF I will begin testing for our full E7500 review.
Better late than never
It's been almost two years since Intel has been in the volume DP server chipset market and a lot of that has to do with their chipset strategy that was introduced late in 1999. Rewinding to the release of the first 0.18-micron Coppermine core based Pentium III processors, the only Intel chipset that supported the 133MHz FSB CPUs was the doomed i820.
In fact, with the exception of their entry-level i810 line, none of Intel's current generation chipsets at the time had support for memory technologies other than RDRAM. By banking on a quick adaptation of RDRAM which would drive market prices lower, Intel designed their entire chipset line - from desktop to server - around RDRAM based chipsets. Even the Timna project was designed to use RDRAM which partially led to its demise (luckily Banias is slowly shaping up to be an even more formidable entry into that market).
With no high-bandwidth SDRAM platform ready to feed the volume chipset market, Intel had to rely on ServerWorks to supply chipsets for the workstation and server markets while VIA carried the desktop market until the i815 was ready. The reason RDRAM was such a pain to deal with on the server side of things was because of the memory size requirements of many high-end servers. With the introductory prices of RDRAM coming in at close to $1000 for 128MB, outfitting a server farm with 4 - 16GB of memory a piece would easily become financially impossible for most IT departments (even in the IT market of 1999 - 2000). For almost the first year of RDRAM's introduction to the x86 market its pricing was still 3x or more than that of SDRAM, thus making it a no-go for the server market.
As our recent article attempted to explain, Intel's lengthy validation process kept them from just popping out a DDR SDRAM solution. Not only did DDR SDRAM have to go through an incredible amount of validation, but Intel's DDR SDRAM chipsets had to do the same. The release of the i845 with DDR support obviously sped things up quite a bit as now Intel had a fully functional and validated DDR memory controller. And now, the E7500 chipset is the result of even more strenuous validation in multiprocessor configurations.
The Chipset
The E7500 chipset introduces a number of firsts for Intel, all of which are important because they can now become potential technology candidates for future desktop chipsets.
The E7500 Memory Controller Hub (MCH) obviously contains the bulk of the improvements that make the chipset what it is. First and foremost is the introduction of a dual channel (2 x 72-bit ECC) DDR SDRAM memory controller. The memory controller in the E7500 is validated for use with both DDR200 and DDR266 SDRAM however the bus will only operate at 100MHz (DDR200 speeds). This means that although you can use DDR266 SDRAM in it, your memory will always run at DDR200 speeds. Intel's reasoning behind this that dual DDR200 channels yield a theoretical 3.2GB/s of bandwidth to main memory which is perfectly matched up to the 3.2GB/s FSB. As we've seen in the past (take the KT133A chipset for example), a synchronized FSB and memory bus generally yields lower latency CPU/memory accesses than an asynchronous setup. It is very clear however that when Intel does move to a 133MHz (533MHz quad-pumped) FSB, a future successor to the E7500 chipset will support DDR266 SDRAM.
The E7500 MCH supports up to 16GB of DDR200 SDRAM through its 8 memory banks; but since it is a dual channel DDR SDRAM solution memory must be installed in pairs of two.
The I/O subsystem of the chipset is also improved with the introduction of Intel's first Hub-Link 2.0 interconnects. Intel first introduced their IHA (Intel Hub Architecture) with the i810 chipset as a replacement to the age-old North/South Bridge chipset architecture. The "hubs" as Intel likes to call them of a chipset were connected by a Hub Link interconnect that was essentially a high-speed serial bus. All current Intel chipsets still use the Hub Link 1.0 that was introduced with the i810, an 8-bit 133MHz double-pumped interconnect bus. The E7500 introduces the first Hub Link (HL) 1.5 and 2.0 buses used in an Intel chipset.
The E7500 features three HL 2.0 connections stemming from the MCH, each operating at 266MHz. Each HL 2.0 interconnect is 2-bytes wide (16-bits) thus resulting in a maximum of 1.06GB/s of bandwidth between the MCH and all devices attached to the bus. Since there are three HL 2.0 buses, a total of 3.2GB/s of I/O bandwidth is theoretically sustainable although reality will never come close to even matching that, much less exceeding it.
What purpose would these three HL 2.0 links serve? With most high-end server applications (e.g. database serving) demanding very high performance I/O subsystems including multidrive RAID arrays and Gigabit Ethernet, eating up bandwidth is a simple task. You'll find a number of E7500 platforms paired with Intel's P64H2 64-bit PCI/PCI-X controller which supports two 64-bit/133MHz PCI-X segments per controller. The P64H2 interfaces directly with HL 2.0 and thus a maximum of three of these chips can be used with an E7500 MCH, resulting in a maximum of six PCI/PCI-X buses. This type of I/O flexibility was previously only reserved for ServerWorks platforms but is greatly welcome and appreciated by the market in an Intel chipset.
From left to right: Two Intel gigabit Ethernet controllers, P64H2 controller, E7500 MCH
To round things off, the E7500 features legacy support through its I/O Controller Hub (ICH). The ICH used with the E7500 is ICH3-S which works on a HL 1.5 link. The only difference between HL 1.5 and HL 1.0 is that it is electrically compatible with HL 2.0 which simplifies design and layout for motherboard manufacturers.
Motherboard Support: Not just Tyan anymore
In the past the vast majority of Taiwanese motherboard manufacturers wouldn't dare come close to touching the high-end server market. Recently, as the desktop market continues to grow more competitive, most Taiwanese firms originally thought of as exclusively desktop board providers are now looking to the high-end server and workstation markets to increase revenues.
There is obviously much less competition in these markets since there are fewer players, but the stakes are also considerably higher. The failure rate of the majority of desktop motherboards we review is simply unacceptable for these high-end markets. Validation processes must also be improved tremendously if these manufacturers are going to be taken seriously in the server market. To get an idea of what manufacturers are announcing support for the E7500 chipset, take a look at Intel's own slide from their E7500/Xeon Server press presentation:
Who would've ever expected to see names like ABIT and QDI alongside Intel's Enterprise Platforms & Services Division, Supermicro and Tyan in a server platform presentation? It's a drastically changing market and those who adapt are those that will succeed but as we've mentioned before, the rules of the game are much different in the server world. Having an on-board IDE RAID controller with compatibility problems or not being able to operate flawlessly with all DIMM slots populated will definitely not fly among the high-spending server customers. While we'll review some of these platforms the true tests of stability and reliability will be unfortunately made outside of our lab once these solutions get into the hands of customers. Let's hope that these E7500 platforms from ABIT, Gigabyte, MSI and QDI come off of a different production line than their desktop motherboards as they will require a much higher degree of care and attention.
Click to Enlarge - Gigabyte's E7500 Board
Should these companies do very well in their volume DP server motherboards then it definitely means trouble for the Tyans and Supermicros of the world that have made their bread and butter almost solely from this market. Then again, it took years of perfection of validation and testing processes to get those two to where they are today and it will take even more effort to compete with them.
Dual Channel DDR on the desktop?
When RDRAM was first introduced to Intel's product line one of the few attractive solutions was the i840 chipset with its dual-channel RDRAM memory controller. Originally aimed at the server/workstation market, this memory subsystem eventually made its way down to the desktop level with the i850 Pentium 4 chipset around one year later.
The correlation we're trying to drive at here relates to the possibility of this dual channel DDR memory controller coming down to the desktop market. Obviously this depends on a number of variables including RDRAM pricing and board design complexity, but it is a possibility that we should keep in mind. It may be an explanation of why NVIDIA still doesn't have a Pentium 4 bus license for their dual channel DDR nForce platform.
Final Words
With IDF this week there will undoubtedly be a number of interesting announcements to read about so be sure to check back all this week for the latest straight from the show. Also, I'll be doing some show coverage on CNet Radio Wednesday (2/27/2002) at 11AM PST so be sure to tune in if you can.
Have a great week.